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a2abfb44ae8520a95dba7be9beba0d4f677a4895
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114 Commits

Author SHA1 Message Date
iceman1001
a2abfb44ae correction of text 2020-10-01 23:48:32 +02:00
Philippe Teuwen
c03e26cf57 Revert "tune stype exceptions" 
This reverts commit aff439953f.
 2020-08-13 12:48:46 +02:00
Philippe Teuwen
aff439953f tune stype exceptions 2020-08-13 12:33:27 +02:00
Philippe Teuwen
4ed57c7c4d make style 2020-08-13 12:25:04 +02:00
iceman1001
ec1c72d73c fix felica image 2020-07-08 23:11:11 +02:00
iceman1001
2c0f595f86 no more snooping around 2020-07-03 14:59:10 +02:00
iceman1001
e2f0f08202 added felica bit file 2020-07-02 11:52:16 +02:00
iceman1001
fdd0487c37 updated bit files 2020-07-02 11:51:52 +02:00
iceman1001
da947affeb felica fpga scr file 2020-07-02 11:51:07 +02:00
iceman1001
59836bbb3b remove 2020-07-02 11:50:01 +02:00
iceman1001
081f397ed7 remove 2020-07-02 11:49:46 +02:00
iceman1001
41dde3281d add files 2020-07-02 11:49:22 +02:00
iceman1001
8df14408b8 fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created. 2020-07-02 11:47:46 +02:00
iceman1001
3f0f08ffbb updated fpga lf image for hitag 2020-02-22 13:34:52 +01:00
Philippe Teuwen
af7fb17607 plotedge script: warn for numpy, matplotlib 2020-02-21 16:10:18 +01:00
Philippe Teuwen
15b661dbfb plot_edgedetect.py converted to python3 2020-02-21 15:36:12 +01:00
iceman1001
d6f552e856 assign direct 2020-01-28 22:06:40 +01:00
iceman1001
6fa188062c style 2020-01-12 17:30:29 +01:00
iceman1001
2e37c04a15 Add: 'hf plot' - implement function from offical repo (piwi) 2020-01-12 15:33:06 +01:00
iceman1001
e4bd3544d5 style 2020-01-12 00:31:08 +01:00
iceman1001
621eb12976 fix: lf simulation, wrong offsets in majormode 2020-01-12 00:30:23 +01:00
iceman1001
5b7882fc4f style 2020-01-12 00:19:12 +01:00
iceman1001
442bab0706 style 2020-01-12 00:18:34 +01:00
iceman1001
05f2fbc75a hitag adaptations (@anon) 2020-01-01 20:52:32 +01:00
iceman1001
9f02aeb85e style 2020-01-01 20:46:51 +01:00
iceman1001
e84f3bb467 add hf plot fpga stuff (@piwi) 2020-01-01 20:44:51 +01:00
iceman1001
21ffdec1cd chg: hitag refactoring (@anon) 2020-01-01 18:18:34 +01:00
osboxes.org
33436ae2c2 rmdir soft 2019-12-31 22:25:50 +01:00
Philippe Teuwen
4fdb5a2f4b make install: half way 2019-08-30 21:55:13 +02:00
Iceman
3cf64f9f23 fix: some mkdir stuff.. 2019-08-21 16:49:32 +02:00
Philippe Teuwen
847b6bcc33 remove tabs 2019-08-13 17:51:11 +02:00
Philippe Teuwen
d19754567d summer restructuring: 
* .h include only the strict minimum for their own parsing
  * this forces all files to include explicitment their needs and not count on far streched dependencies
  * this helps Makefile to rebuild only the minimum
  * according to this rule, most standalone .h are now gone
  * big app.h is gone
  * remove seldom __cplusplus, if c++ happens, everything will have to be done properly anyway
* all unrequired include were removed
* split common/ into common/ (client+arm) and common_arm/ (os+bootloader)
  * bring zlib to common/
  * bring stuff not really/not yet used in common back to armsrc/ or client/
  * bring liblua into client/
  * bring uart into client/
  * move some portions of code around (dbprint, protocols,...)
* rename unused files into *_disabled.[ch] to make it explicit
* rename soft Uarts between 14a, 14b and iclass, so a standalone could use several without clash
* remove PrintAndLogDevice
* move deprecated-hid-flasher from client to tools
* Makefiles
  * treat deps in armsrc/ as in client/
  * client: stop on warning (-Werror), same as for armsrc/

Tested on:

* all standalone modes
* Linux
 2019-08-11 21:42:01 +02:00
Philippe Teuwen
1354aec556 typos 2019-08-06 13:51:10 +02:00
iceman1001
2400418067 style 2019-08-01 11:15:39 -04:00
iceman1001
141ab65f78 chg: compiled binary fpga lf 2019-07-31 16:14:50 +02:00
iceman1001
774c8dd666 Add: 'fpga LF ADC path' - a major mode for LF ADC path 2019-07-31 15:50:10 +02:00
Philippe Teuwen
cb439ef58b style of .v files 2019-07-30 22:51:38 +02:00
Philippe Teuwen
8c0cd4cfa2 Cleaner makefile execution, use 'make Q=' if you want to see full lines 2019-06-02 00:25:25 +02:00
Philippe Teuwen
84f696451d units 2019-05-09 01:07:34 +02:00
iceman1001
1033b67f3c chg: fpga lf simulation 2019-04-18 09:41:31 +02:00
iceman1001
72dd4d5dde chg: 'fpga lf sim' - 25% both on sides. 2019-04-18 09:27:38 +02:00
Philippe Teuwen
2f12e57408 Makefiles: remove spurious spaces/tabs 2019-03-10 11:35:03 +01:00
Philippe Teuwen
46af10d54d scripts: fix mix of spaces & tabs 2019-03-09 11:10:22 +01:00
Chris
1d51b2cd8f fix: variable name 
textual
 2018-09-08 14:15:05 +02:00
Chris
79afc031fc FIX: LF antenna discharge after interfer timings. As suggested by @ts And thanks to @drandreas who patiently explains fpga verilog code to me. 
This introduces a new majoe mode, FPGA_MAJOR_MODE_OFF_LF,  which should ONLY be used in sending loops for LF.   Basically the PWR_LO is set HIGH in order to discharge voltage faster.

Once sending is over,  the normal FPGA_MAJOR_MODE_OFF SHALL be used.
 2018-09-08 14:11:51 +02:00
AntiCat
e472a21194 FPGA Hi-Simulate: Added 212kHz SSP-Clock option 2018-09-05 23:01:55 +02:00
AntiCat
0994c91888 FPGA Hi-Simulate: Freed up 4 LUTs 2018-09-05 23:01:55 +02:00
AntiCat
cef5dc4e83 FPGA Hi-Simulate: Fixed documantation 2018-09-05 23:01:55 +02:00
AntiCat
6ca899d130 FPGA Hi-Simulate: Formatted code 2018-09-05 23:01:55 +02:00
Andreas Dröscher
bf123082e8 change: remove jerry-riged hysteresis based receiver from hi_read_tx 
This future got obsolete by a x-correlation based receiver.

This reverts commit 24fe4dffb4.
 2018-08-12 09:59:48 +02:00