style

fpga/lo_adc.v

@@ -32,9 +32,9 @@ reg [7:0] pck_divider;
 reg clk_state;
 
 // Antenna logic, depending on "lf_field" (in arm defined as FPGA_LF_READER_FIELD)
-wire tag_modulation; 
+wire tag_modulation;
 assign tag_modulation = ssp_dout & !lf_field;
-wire reader_modulation; 
+wire reader_modulation;
 assign reader_modulation = !ssp_dout & lf_field & clk_state;
 assign pwr_oe1 = 1'b0; // not used in LF mode
 assign pwr_oe2 = 1'b0; //tag_modulation;