units

2019-05-09 01:07:34 +02:00
parent 2c10482279
commit 84f696451d
8 changed files with 17 additions and 17 deletions
--- a/fpga/hi_simulate.v
+++ b/fpga/hi_simulate.v
@@ -63,7 +63,7 @@ reg ssp_clk;
 always @(negedge adc_clk)
 begin
    if(mod_type == 3'b101)
-      // Get bit every at 53KHz (every 8th carrier bit of 424kHz)
+      // Get bit every at 53kHz (every 8th carrier bit of 424kHz)
      ssp_clk <= ssp_clk_divider[7];
    else if(mod_type == 3'b010)
      // Get next bit at 212kHz