fix: legic functionality for RDV40. Getting 2-3cm reading distances now.
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fpga/fpga_hf.bit
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fpga/fpga_hf.bit
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@@ -79,13 +79,11 @@ assign adc_clk = ck_1356meg;
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reg after_hysteresis;
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always @(negedge adc_clk)
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begin
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if(& adc_d[7:0]) after_hysteresis <= 1'b1;
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else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
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if(& adc_d[6:4]) after_hysteresis <= 1'b1;
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else if(~(| adc_d[6:4])) after_hysteresis <= 1'b0;
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end
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assign ssp_din = after_hysteresis;
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assign dbg = ssp_din;
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assign dbg = after_hysteresis;
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endmodule
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