FIX: LF antenna discharge after interfer timings. As suggested by @ts And thanks to @drandreas who patiently explains fpga verilog code to me.

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This introduces a new majoe mode, FPGA_MAJOR_MODE_OFF_LF,  which should ONLY be used in sending loops for LF.   Basically the PWR_LO is set HIGH in order to discharge voltage faster.

Once sending is over,  the normal FPGA_MAJOR_MODE_OFF SHALL be used.

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Chris

2018-09-08 14:11:51 +02:00

parent 56f3ef2a55

commit 79afc031fc

4 changed files with 20 additions and 15 deletions

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