diff --git a/armsrc/fpgaloader.h b/armsrc/fpgaloader.h
index 21731b571..a1e0d1ee0 100644
--- a/armsrc/fpgaloader.h
+++ b/armsrc/fpgaloader.h
@@ -62,7 +62,9 @@ extern void switch_off(void);
 #define FPGA_MAJOR_MODE_HF_SNOOP				    (4<<5)
 #define FPGA_MAJOR_MODE_HF_FELICA      				(5<<5)
 // BOTH
+#define FPGA_MAJOR_MODE_OFF_LF						(6<<5)
 #define FPGA_MAJOR_MODE_OFF							(7<<5)
+
 // Options for LF_ADC
 #define FPGA_LF_ADC_READER_FIELD					(1<<0)
 // Options for LF_EDGE_DETECT
@@ -76,11 +78,11 @@ extern void switch_off(void);
 #define FPGA_HF_READER_RX_XCORR_SNOOP				(1<<1)
 #define FPGA_HF_READER_RX_XCORR_QUARTER				(1<<2)
 // Options for the HF simulated tag, how to modulate
-#define FPGA_HF_SIMULATOR_NO_MODULATION				(0<<0) // 0000
-#define FPGA_HF_SIMULATOR_MODULATE_BPSK				(1<<0) // 0001
-#define FPGA_HF_SIMULATOR_MODULATE_212K				(2<<0) // 0010
-#define FPGA_HF_SIMULATOR_MODULATE_424K				(4<<0) // 0100
-#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT		0x5    // 0101
+#define FPGA_HF_SIMULATOR_NO_MODULATION				0x0 // 0000
+#define FPGA_HF_SIMULATOR_MODULATE_BPSK				0x1 // 0001
+#define FPGA_HF_SIMULATOR_MODULATE_212K				0x2 // 0010
+#define FPGA_HF_SIMULATOR_MODULATE_424K				0x4 // 0100
+#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT		0x5 // 0101
 //  no 848K 
 
 // Options for ISO14443A
diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 9d6cfbf0e..a957e4dfb 100644
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -26,10 +26,9 @@
 # define OPEN_COIL()	HIGH(GPIO_SSC_DOUT)
 #endif
 
-
-#define START_GAP 52*8 // was 250 // SPEC:  1*8 to 50*8 - typ 15*8 (15fc)
-#define WRITE_GAP 18*8 // was 160 // SPEC:  1*8 to 20*8 - typ 10*8 (10fc)
-#define WRITE_0   24*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
+#define START_GAP 31*8 // was 250 // SPEC:  1*8 to 50*8 - typ 15*8 (15fc)
+#define WRITE_GAP 20*8 // was 160 // SPEC:  1*8 to 20*8 - typ 10*8 (10fc)
+#define WRITE_0   18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
 #define WRITE_1   54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc)  432 for T55x7; 448 for E5550
 #define READ_GAP  15*8 
 
@@ -1260,7 +1259,7 @@ void TurnReadLFOn(uint32_t delay) {
 	WaitUS(delay);
 }
 void TurnReadLF_off(uint32_t delay) {
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
 	WaitUS(delay);
 }
 
diff --git a/fpga/fpga_lf.bit b/fpga/fpga_lf.bit
index 44ef60365..7d9a840a3 100644
Binary files a/fpga/fpga_lf.bit and b/fpga/fpga_lf.bit differ
diff --git a/fpga/fpga_lf.v b/fpga/fpga_lf.v
index 1b7a11276..3082b037b 100644
--- a/fpga/fpga_lf.v
+++ b/fpga/fpga_lf.v
@@ -104,15 +104,19 @@ lo_edge_detect le(
 //   000 --  LF reader (generic)
 //   001 --  LF edge detect (generic)
 //   010 --  LF passthrough
-
-mux8 mux_ssp_clk		(major_mode, ssp_clk,   lr_ssp_clk,   le_ssp_clk,         1'b0,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
-mux8 mux_ssp_din		(major_mode, ssp_din,   lr_ssp_din,         1'b0,   lp_ssp_din,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
-mux8 mux_ssp_frame		(major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame,       1'b0,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
+/*
+FPGA_MAJOR_MODE_OFF_LF	(6<<5)
+FPGA_MAJOR_MODE_OFF		(7<<5)
+*/
+//                                              000           001           010           011   100   101   110   111
+mux8 mux_ssp_clk		(major_mode, ssp_clk,   lr_ssp_clk,   le_ssp_clk,   1'b0,         1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_ssp_din		(major_mode, ssp_din,   lr_ssp_din,   1'b0,         lp_ssp_din,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
+mux8 mux_ssp_frame		(major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0,         1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
 mux8 mux_pwr_oe1		(major_mode, pwr_oe1,   lr_pwr_oe1,   le_pwr_oe1,   lp_pwr_oe1,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
 mux8 mux_pwr_oe2		(major_mode, pwr_oe2,   lr_pwr_oe2,   le_pwr_oe2,   lp_pwr_oe2,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
 mux8 mux_pwr_oe3		(major_mode, pwr_oe3,   lr_pwr_oe3,   le_pwr_oe3,   lp_pwr_oe3,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
 mux8 mux_pwr_oe4		(major_mode, pwr_oe4,   lr_pwr_oe4,   le_pwr_oe4,   lp_pwr_oe4,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
-mux8 mux_pwr_lo			(major_mode, pwr_lo,    lr_pwr_lo,    le_pwr_lo,    lp_pwr_lo,    1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
+mux8 mux_pr_lo			(major_mode, pwr_lo,    lr_pwr_lo,    le_pwr_lo,    lp_pwr_lo,    1'b0, 1'b0, 1'b0, 1'b1, 1'b0); 
 mux8 mux_pwr_hi			(major_mode, pwr_hi,    lr_pwr_hi,    le_pwr_hi,    lp_pwr_hi,    1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
 mux8 mux_adc_clk		(major_mode, adc_clk,   lr_adc_clk,   le_adc_clk,   lp_adc_clk,   1'b0, 1'b0, 1'b0, 1'b0, 1'b0); 
 mux8 mux_dbg			(major_mode, dbg,       lr_dbg,       le_dbg,       lp_dbg,       1'b0, 1'b0, 1'b0, 1'b0, 1'b0);