Avoid first spurious samples in LF sniff modes, prevents false triggering
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@@ -243,8 +243,11 @@ void LFSetupFPGAForADC(int divisor, bool reader_field) {
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StartTicks();
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// 50ms for the resonant antenna to settle.
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if (reader_field)
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if (reader_field) {
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WaitMS(50);
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} else {
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WaitMS(1);
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}
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}
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/**
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