CHG: bootrom configuration to highest clock PLL

2017-09-26 17:04:53 +02:00
parent b18920b9f9
commit 07fffb4645
1 changed files with 2 additions and 1 deletions
--- a/bootrom/bootrom.c
+++ b/bootrom/bootrom.c
@@ -55,7 +55,8 @@ static void ConfigClocks(void) {
    // PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
    AT91C_BASE_PMC->PMC_PLLR =
    	PMC_PLL_DIVISOR(2) |
-		PMC_PLL_COUNT_BEFORE_LOCK(0x10) |
+		//PMC_PLL_COUNT_BEFORE_LOCK(0x10) |
+		PMC_PLL_COUNT_BEFORE_LOCK(0x3F) |
 		PMC_PLL_FREQUENCY_RANGE(0) |
 		PMC_PLL_MULTIPLIER(12) |
 		PMC_PLL_USB_DIVISOR(1);