Philippe Teuwen 84f696451d units

2019-05-09 01:07:34 +02:00

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tests

Makefiles: remove spurious spaces/tabs

2019-03-10 11:35:03 +01:00

clk_divider.v

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fpga_hf.bit

FPGA Hi-Simulate: Added 212kHz SSP-Clock option

2018-09-05 23:01:55 +02:00

fpga_hf.v

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fpga_lf.bit

chg: fpga lf simulation

2019-04-18 09:41:31 +02:00

fpga_lf.v

fix: variable name

2018-09-08 14:15:05 +02:00

fpga.ucf

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go.bat

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hi_flite.v

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hi_iso14443a.v

CHG: Thanks to @pwpiwi , his latest adjustments to HF.

2017-11-10 19:51:37 +01:00

hi_read_rx_xcorr.v

change: fixed xcorrelation for strong signal

2018-08-10 02:36:04 +02:00

hi_read_tx.v

change: remove jerry-riged hysteresis based receiver from hi_read_tx

2018-08-12 09:59:48 +02:00

hi_simulate.v

units

2019-05-09 01:07:34 +02:00

hi_sniffer.v

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lf_edge_detect.v

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lo_edge_detect.v

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lo_passthru.v

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lo_read.v

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lo_simulate.v

chg: 'fpga lf sim' - 25% both on sides.

2019-04-18 09:27:38 +02:00

lp20khz_1MSa_iir_filter.v

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Makefile

chg: fpga lf simulation

2019-04-18 09:41:31 +02:00

min_max_tracker.v

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sim.tcl

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testbed_fpga.v

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testbed_hi_read_tx.v

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testbed_hi_simulate.v

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testbed_lo_read.v

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testbed_lo_simulate.v

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util.v

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xst_hf.scr

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xst_lf.scr

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xst_nfc.scr

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