iceman1001 1033b67f3c chg: fpga lf simulation

2019-04-18 09:41:31 +02:00

..

tests

Makefiles: remove spurious spaces/tabs

2019-03-10 11:35:03 +01:00

clk_divider.v

…

fpga_hf.bit

FPGA Hi-Simulate: Added 212kHz SSP-Clock option

2018-09-05 23:01:55 +02:00

fpga_hf.v

…

fpga_lf.bit

chg: fpga lf simulation

2019-04-18 09:41:31 +02:00

fpga_lf.v

fix: variable name

2018-09-08 14:15:05 +02:00

fpga.ucf

…

go.bat

…

hi_flite.v

…

hi_iso14443a.v

…

hi_read_rx_xcorr.v

…

hi_read_tx.v

change: remove jerry-riged hysteresis based receiver from hi_read_tx

2018-08-12 09:59:48 +02:00

hi_simulate.v

FPGA Hi-Simulate: Added 212kHz SSP-Clock option

2018-09-05 23:01:55 +02:00

hi_sniffer.v

…

lf_edge_detect.v

…

lo_edge_detect.v

…

lo_passthru.v

…

lo_read.v

…

lo_simulate.v

chg: 'fpga lf sim' - 25% both on sides.

2019-04-18 09:27:38 +02:00

lp20khz_1MSa_iir_filter.v

…

Makefile

chg: fpga lf simulation

2019-04-18 09:41:31 +02:00

min_max_tracker.v

…

sim.tcl

setting svn:eol-style=native on files, part 3

2010-02-22 19:29:05 +00:00

testbed_fpga.v

…

testbed_hi_read_tx.v

…

testbed_hi_simulate.v

…

testbed_lo_read.v

…

testbed_lo_simulate.v

setting svn:eol-style=native on files, part 3

2010-02-22 19:29:05 +00:00

util.v

setting svn:eol-style=native on files, part 3

2010-02-22 19:29:05 +00:00

xst_hf.scr

…

xst_lf.scr

THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.

2014-06-20 01:02:59 +02:00

xst_nfc.scr

…