Philippe Teuwen 491adacb94 get rid of tabs

2020-10-06 20:45:13 +02:00

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tests

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clk_divider.v

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fpga_felica.bit

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fpga_felica.v

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2020-10-06 20:45:13 +02:00

fpga_hf.bit

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fpga_hf.v

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fpga_lf.bit

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fpga_lf.v

correction of text

2020-10-01 23:48:32 +02:00

fpga.ucf

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go.bat

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hi_flite.v

pwr_oe2 is LF

2020-10-02 19:42:19 +02:00

hi_get_trace.v

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hi_iso14443a.v

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hi_reader.v

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hi_simulate.v

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hi_sniffer.v

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lf_edge_detect.v

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lo_adc.v

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lo_edge_detect.v

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lo_passthru.v

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lo_read.v

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lo_simulate.v

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lp20khz_1MSa_iir_filter.v

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Makefile

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min_max_tracker.v

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sim.tcl

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testbed_fpga.v

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testbed_hi_read_tx.v

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testbed_hi_simulate.v

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testbed_lo_read.v

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testbed_lo_simulate.v

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util.v

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xst_felica.scr

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xst_hf.scr

THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.

2014-06-20 01:02:59 +02:00

xst_lf.scr

THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.

2014-06-20 01:02:59 +02:00