iceman1001 8e5a285099 textual

2020-10-02 19:42:47 +02:00

..

tests

…

clk_divider.v

…

fpga_felica.bit

Revert "tune stype exceptions"

2020-08-13 12:48:46 +02:00

fpga_felica.v

make style

2020-08-13 12:25:04 +02:00

fpga_hf.bit

Revert "tune stype exceptions"

2020-08-13 12:48:46 +02:00

fpga_hf.v

correction of text

2020-10-01 23:49:01 +02:00

fpga_lf.bit

Revert "tune stype exceptions"

2020-08-13 12:48:46 +02:00

fpga_lf.v

correction of text

2020-10-01 23:48:32 +02:00

fpga.ucf

…

go.bat

…

hi_flite.v

pwr_oe2 is LF

2020-10-02 19:42:19 +02:00

hi_get_trace.v

…

hi_iso14443a.v

textual

2020-10-02 19:42:47 +02:00

hi_reader.v

make style

2020-08-13 12:25:04 +02:00

hi_simulate.v

make style

2020-08-13 12:25:04 +02:00

hi_sniffer.v

…

lf_edge_detect.v

…

lo_adc.v

…

lo_edge_detect.v

…

lo_passthru.v

…

lo_read.v

…

lo_simulate.v

…

lp20khz_1MSa_iir_filter.v

…

Makefile

…

min_max_tracker.v

…

sim.tcl

…

testbed_fpga.v

…

testbed_hi_read_tx.v

…

testbed_hi_simulate.v

…

testbed_lo_read.v

…

testbed_lo_simulate.v

typos

2019-08-06 13:51:10 +02:00

util.v

…

xst_felica.scr

felica fpga scr file

2020-07-02 11:51:07 +02:00

xst_hf.scr

…

xst_lf.scr

THIS REQUIRES A BOOTROM UPDATE!! To save FPGA area, split the LF and HF bitstreams and load them on-demand.

2014-06-20 01:02:59 +02:00