Philippe Teuwen 491adacb94 get rid of tabs

2020-10-06 20:45:13 +02:00

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tests

plotedge script: warn for numpy, matplotlib

2020-02-21 16:10:18 +01:00

clk_divider.v

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fpga_felica.bit

Revert "tune stype exceptions"

2020-08-13 12:48:46 +02:00

fpga_felica.v

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fpga_hf.bit

Revert "tune stype exceptions"

2020-08-13 12:48:46 +02:00

fpga_hf.v

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fpga_lf.bit

Revert "tune stype exceptions"

2020-08-13 12:48:46 +02:00

fpga_lf.v

correction of text

2020-10-01 23:48:32 +02:00

fpga.ucf

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go.bat

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hi_flite.v

pwr_oe2 is LF

2020-10-02 19:42:19 +02:00

hi_get_trace.v

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hi_iso14443a.v

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hi_reader.v

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hi_simulate.v

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hi_sniffer.v

fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.

2020-07-02 11:47:46 +02:00

lf_edge_detect.v

typos

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lo_adc.v

assign direct

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lo_edge_detect.v

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lo_passthru.v

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lo_read.v

typos

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lo_simulate.v

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lp20khz_1MSa_iir_filter.v

typos

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Makefile

fgpa changes from official repo. Had to split felica into its own image. Leading to three bit files created.

2020-07-02 11:47:46 +02:00

min_max_tracker.v

chg: hitag refactoring (@anon)

2020-01-01 18:18:34 +01:00

sim.tcl

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testbed_fpga.v

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testbed_hi_read_tx.v

typos

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testbed_hi_simulate.v

typos

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testbed_lo_read.v

typos

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testbed_lo_simulate.v

typos

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util.v

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xst_felica.scr

felica fpga scr file

2020-07-02 11:51:07 +02:00

xst_hf.scr

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xst_lf.scr

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