TC1 counts the number of TC0 overflows (carry bits).
In random conditions TC1 would return or stay at zero,
instead of counting up. This due to the behavior of the
reset signal.
SAM7S Series Datasheet, 33.5.6 Trigger:
Regardless of the trigger used, it will be taken into account
at the following active edge of the selected clock. This means
that the counter value can be read differently from zero just
after a trigger, especially when a low frequency signal is
selected as the clock.
The new code first prepares TC1 and asserts TC1 trigger and
then prepares TC0 and asserts TC0 trigger. The TC0 start-up
will reset TC1.
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
- Even tough legic tags transmit just AM using xcorrelation
results in a significantly better signal quality.
- Switching from bit bang to a hardware based ssc frees
up CPU time for other tasks e.g. demodulation
I've tried to modulate the Legic specific pause-puls using ssc and the default
ssc clock of 105.4 kHz (bit periode of 9.4us) - previous commit. However,
the timing was not precise enough. By increasing the ssc clock this could
be circumvented, but the adventage over bitbang would be little.
- Even tough legic tags transmit just AM using xcorrelation
results in a significantly better signal quality.
- Switching from bit bang to a hardware based ssc frees
up CPU time for other tasks e.g. demodulation
chg: 'hf 14a info' - tag identification for FM11RF005SH (@maozhenyu123)
Fudan FM11RF005SH , has 512bit mem, 16blocks w 4bytes / block.
Support REQA, READ, WRITE, AUTH. Unknown how the auth is done.
The ATQA/SAK , or a trace from one of these tags would be intersting to look at.
