chg: revert fpga_major mode in LF.
chg: 'lf t55xx deviceconfig' - persistence to flashmem is now option with param P
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@@ -70,7 +70,7 @@ void printT55xxConfig(void) {
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Dbprintf(" [e] readgap.............%d*8 (%d)", t_config.read_gap/8, t_config.read_gap);
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}
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void setT55xxConfig(t55xx_config *c) {
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void setT55xxConfig(uint8_t arg0, t55xx_config *c) {
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if (c->start_gap != 0) t_config.start_gap = c->start_gap;
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if (c->write_gap != 0) t_config.write_gap = c->write_gap;
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@@ -81,24 +81,36 @@ void setT55xxConfig(t55xx_config *c) {
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printT55xxConfig();
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#if WITH_FLASH
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// shall persist to flashmem
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if (arg0 == 0) {
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return;
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}
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if (!FlashInit()) {
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return;
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}
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uint8_t buf[T55XX_CONFIG_LEN];
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uint8_t *buf = BigBuf_malloc(4096);
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Flash_CheckBusy(BUSY_TIMEOUT);
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uint16_t res = Flash_ReadDataCont(T55XX_CONFIG_OFFSET, buf, 4096);
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if ( res == 0) {
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FlashStop();
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BigBuf_free();
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return;
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}
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memcpy(buf, &t_config, T55XX_CONFIG_LEN);
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Flash_CheckBusy(BUSY_TIMEOUT);
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Flash_WriteEnable();
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uint16_t isok = Flash_WriteDataCont(T55XX_CONFIG_OFFSET, buf, sizeof(buf));
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FlashStop();
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Flash_WriteEnable();
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Flash_Erase4k(3, 0xD);
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res = Flash_Write(T55XX_CONFIG_OFFSET, buf, 4096);
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if ( isok == T55XX_CONFIG_LEN) {
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if (MF_DBGLEVEL > 1) {
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DbpString("T55XX Config save success");
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Dbhexdump(sizeof(buf), buf, false);
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}
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if ( res == 4096 && MF_DBGLEVEL > 1) {
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DbpString("T55XX Config save success");
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}
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BigBuf_free();
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#endif
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}
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@@ -139,7 +151,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint
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// Make sure the tag is reset
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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WaitMS(500);
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// clear read buffer
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@@ -180,7 +192,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint
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if (command[counter] == '0') {
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// if field already off leave alone (affects timing otherwise)
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if (off == false) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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LED_D_OFF();
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off = true;
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}
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@@ -207,7 +219,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint
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TurnReadLFOn(period_1);
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LED_D_OFF();
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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WaitUS(delay_off);
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}
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@@ -1328,7 +1340,7 @@ void TurnReadLFOn(uint32_t delay) {
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WaitUS(delay);
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}
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void TurnReadLF_off(uint32_t delay) {
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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WaitUS(delay);
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}
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@@ -1338,7 +1350,7 @@ void T55xxWriteBit(int bit) {
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TurnReadLFOn(t_config.write_0);
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else
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TurnReadLFOn(t_config.write_1);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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WaitUS(t_config.write_gap);
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}
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@@ -1356,7 +1368,7 @@ void T55xxResetRead(void) {
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WaitMS(4);
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// Trigger T55x7 in mode.
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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WaitUS(t_config.start_gap);
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// reset tag - op code 00
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@@ -1390,7 +1402,7 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg)
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// make sure tag is fully powered up...
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WaitMS(4);
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// Trigger T55x7 in mode.
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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WaitUS(t_config.start_gap);
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if (testMode) Dbprintf("TestMODE");
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@@ -1475,7 +1487,7 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
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// make sure tag is fully powered up...
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WaitMS(4);
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// Trigger T55x7 Direct Access Mode with start gap
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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WaitUS(t_config.start_gap);
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// Opcode 1[page]
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@@ -1522,7 +1534,7 @@ void T55xxWakeUp(uint32_t Pwd){
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WaitMS(4);
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// Trigger T55x7 Direct Access Mode
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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WaitUS(t_config.start_gap);
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// Opcode 10
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@@ -1962,7 +1974,7 @@ This triggers a COTAG tag to response
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*/
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void Cotag(uint32_t arg0) {
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#ifndef OFF
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# define OFF { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF_LF); WaitUS(2035); }
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# define OFF { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2035); }
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#endif
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#ifndef ON
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# define ON(x) { FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); WaitUS((x)); }
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