assign direct
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@@ -29,11 +29,8 @@ reg [7:0] pck_divider;
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reg clk_state;
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reg clk_state;
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// Antenna logic, depending on "lf_field" (in arm defined as FPGA_LF_READER_FIELD)
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// Antenna logic, depending on "lf_field" (in arm defined as FPGA_LF_READER_FIELD)
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wire tag_modulation;
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wire tag_modulation = ssp_dout & !lf_field;
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assign tag_modulation = ssp_dout & !lf_field;
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wire reader_modulation = !ssp_dout & lf_field & clk_state;
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wire reader_modulation;
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assign reader_modulation = !ssp_dout & lf_field & clk_state;
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// always on (High Frequency outputs, unused)
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// always on (High Frequency outputs, unused)
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assign pwr_oe1 = 1'b0;
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assign pwr_oe1 = 1'b0;
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