style of .v files

fpga/lo_read.v

@@ -8,13 +8,13 @@
 //-----------------------------------------------------------------------------
 
 module lo_read(
-	input pck0, input [7:0] pck_cnt, input pck_divclk,
-	output pwr_lo, output pwr_hi,
-	output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
-	input [7:0] adc_d, output adc_clk,
-	output ssp_frame, output ssp_din, output ssp_clk,
-	output dbg,
-	input lf_field
+    input pck0, input [7:0] pck_cnt, input pck_divclk,
+    output pwr_lo, output pwr_hi,
+    output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
+    input [7:0] adc_d, output adc_clk,
+    output ssp_frame, output ssp_din, output ssp_clk,
+    output dbg,
+    input lf_field
 );
 
 reg [7:0] to_arm_shiftreg;
@@ -27,17 +27,17 @@ reg [7:0] to_arm_shiftreg;
 // we read the ADC value when pck_cnt=7 and shift it out on counts 8..15
 always @(posedge pck0)
 begin
-	if((pck_cnt == 8'd7) && !pck_divclk)
-		to_arm_shiftreg <= adc_d;
-	else begin
-		to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
-		// simulation showed a glitch occuring due to the LSB of the shifter
-		// not being set as we shift bits out
-		// this ensures the ssp_din remains low after a transfer and suppresses
-		// the glitch that would occur when the last data shifted out ended in
-		// a 1 bit and the next data shifted out started with a 0 bit
-		to_arm_shiftreg[0] <= 1'b0;
-	end
+    if((pck_cnt == 8'd7) && !pck_divclk)
+        to_arm_shiftreg <= adc_d;
+    else begin
+        to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
+        // simulation showed a glitch occuring due to the LSB of the shifter
+        // not being set as we shift bits out
+        // this ensures the ssp_din remains low after a transfer and suppresses
+        // the glitch that would occur when the last data shifted out ended in
+        // a 1 bit and the next data shifted out started with a 0 bit
+        to_arm_shiftreg[0] <= 1'b0;
+    end
 end
 
 // ADC samples on falling edge of adc_clk, data available on the rising edge