style of .v files

fpga/lo_edge_detect.v

@@ -35,11 +35,11 @@ wire tag_modulation = ssp_dout & !lf_field;
 wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
 
 // No logic, straight through.
-assign pwr_oe1 = 1'b0; 						// not used in LF mode 
-assign pwr_oe3 = 1'b0; 						// base antenna load = 33 Ohms
+assign pwr_oe1 = 1'b0;                      // not used in LF mode
+assign pwr_oe3 = 1'b0;                      // base antenna load = 33 Ohms
 // when modulating, add another 33 Ohms and 10k Ohms in parallel:
 assign pwr_oe2 = tag_modulation;
-assign pwr_oe4 = tag_modulation; 
+assign pwr_oe4 = tag_modulation;
 
 assign ssp_clk = cross_lo;
 assign pwr_lo = reader_modulation;
@@ -56,9 +56,9 @@ wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
 wire [7:0] max, min;
 wire edge_state, edge_toggle;
 lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
-	max, min,
-	high_threshold, highz_threshold, lowz_threshold, low_threshold,
-	edge_state, edge_toggle);
+    max, min,
+    high_threshold, highz_threshold, lowz_threshold, low_threshold,
+    edge_state, edge_toggle);
 
 assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;