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CHG: syntax suger

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This commit is contained in:
iceman1001
2016-10-10 21:53:44 +02:00
parent f8ff1483eb
commit c7b4bcc4ab
1 changed files with 3 additions and 4 deletions
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7
armsrc/iso14443b.c
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@@ -453,7 +453,7 @@ static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len) {
StartCountSspClk(); StartCountSspClk();
volatile uint8_t b; volatile uint8_t b = 0;
// clear receiving shift register and holding register // clear receiving shift register and holding register
// What does this loop do? Is it TR1? // What does this loop do? Is it TR1?
@@ -467,7 +467,6 @@ static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len) {
// Now run a `software UART' on the stream of incoming samples. // Now run a `software UART' on the stream of incoming samples.
UartInit(received); UartInit(received);
b = 0;
uint8_t mask; uint8_t mask;
while( !BUTTON_PRESS() ) { while( !BUTTON_PRESS() ) {
WDT_HIT(); WDT_HIT();
@@ -490,11 +489,11 @@ void ClearFpgaShiftingRegisters(void){
volatile uint8_t b; volatile uint8_t b;
// clear receiving shift register and holding register // clear receiving shift register and holding register
while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)); while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)) {};
b = AT91C_BASE_SSC->SSC_RHR; (void) b; b = AT91C_BASE_SSC->SSC_RHR; (void) b;
while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)); while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)) {};
b = AT91C_BASE_SSC->SSC_RHR; (void) b; b = AT91C_BASE_SSC->SSC_RHR; (void) b;