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chg: 'fpga lf sim' - 25% both on sides.

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iceman1001
2019-04-18 09:27:38 +02:00
parent 587d826f84
commit 72dd4d5dde
1 changed files with 1 additions and 1 deletions
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fpga/lo_simulate.v
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@@ -64,7 +64,7 @@ reg output_state;
always @(posedge pck0) always @(posedge pck0)
begin begin
if((pck_divider == 8'd7) && !clk_state) begin if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd200); is_high = (adc_d >= 8'd191);
is_low = (adc_d <= 8'd64); is_low = (adc_d <= 8'd64);
end end
end end