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Legic: Moved card simulator into separate file & cleaned interface.

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Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
This commit is contained in:
AntiCat
2018-09-05 22:23:25 +02:00
parent e472a21194
commit 61e4eac2b2
7 changed files with 176 additions and 24 deletions
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armsrc/Makefile
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@@ -54,7 +54,7 @@ SRC_FELICA = felica.c
SRC_CRAPTO1 = crypto1.c des.c aes.c desfire_key.c desfire_crypto.c mifaredesfire.c
SRC_CRC = crc.c crc16.c crc32.c
SRC_ICLASS = iclass.c optimized_cipher.c
SRC_LEGIC = legicrf.c legic_prng.c
SRC_LEGIC = legicrf.c legicrfsim.c legic_prng.c
SRC_BEE = bee.c
# RDV40 related hardware support