ADD: lf cotag - added first try at basic functionality to read samples from Cotag. In lfops.c is the startup sequence that needs to be tested out.
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@@ -1009,6 +1009,9 @@ void UsbPacketReceived(uint8_t *packet, int len)
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case CMD_VIKING_CLONE_TAG:
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CopyVikingtoT55xx(c->arg[0], c->arg[1], c->arg[2]);
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break;
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case CMD_COTAG:
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Cotag();
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break;
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#endif
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#ifdef WITH_HITAG
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@@ -98,6 +98,7 @@ void T55xxWakeUp(uint32_t Pwd);
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void TurnReadLFOn(uint32_t delay);
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void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode);
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void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode);
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void Cotag();
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/// iso14443b.h
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void SimulateIso14443bTag(uint32_t pupi);
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@@ -1737,3 +1737,49 @@ void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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LED_D_OFF();
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}
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void Cotag() {
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#define WAIT2200 { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2200); }
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LED_A_ON();
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//clear buffer now so it does not interfere with timing later
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BigBuf_Clear_keep_EM();
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// Set up FPGA, 132kHz to power up the tag
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FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
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FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 89);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
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// Connect the A/D to the peak-detected low-frequency path.
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SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
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// 50ms for the resonant antenna to settle.
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SpinDelay(50);
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// Now set up the SSC to get the ADC samples that are now streaming at us.
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FpgaSetupSsc();
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// start a 1.5ticks is 1us
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StartTicks();
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//send start pulse
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TurnReadLFOn(800);
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WAIT2200
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TurnReadLFOn(3600);
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WAIT2200
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TurnReadLFOn(800);
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WAIT2200
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TurnReadLFOn(3600);
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// Turn field on to read the response
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TurnReadLFOn(READ_GAP);
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// Acquisition
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doT55x7Acquisition(20000);
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// Turn the field off
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
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cmd_send(CMD_ACK,0,0,0,0,0);
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LED_A_OFF();
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}
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